The present disclosure relates generally to integrated circuits (ICs), which may include programmable logic devices (PLDs) such as field programmable gate arrays (FPGAs). More particularly, the present disclosure relates to visualizing and analyzing a chip view including numerous circuit design revisions to be potentially implemented on the ICs.
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Integrated circuits (ICs) take a variety of forms. For instance, programmable logic devices (PLDs) such as field programmable gate arrays (FPGAs) are ICs that may be highly flexible devices. FPGAs include logic that may be programmed after manufacturing to provide functionality that the FPGA may be designed to support. Thus, FPGAs contain programmable logic, or combinational logic blocks, that may perform a variety of functions on the FPGAs, according to a circuit design of a user. In a programmable logic circuit design, groups of combinational logic elements may be separated by registers. At each clock cycle, a data signal may exit one register, be processed through a first group of combinational logic elements, and enter another register to wait for the next clock cycle to begin. At the next clock cycle, the data signal may continue through a second group of combinational logic elements into a third register, and so forth. Thus, the way that the registers separate different groups of combinational logic elements may have a substantial impact on the maximum achievable clock signal frequency by which the data signal may pass through the programmable logic circuit design. The maximum clock signal frequency may depend on how quickly the data signal can pass through a group of combinational logic elements between any two registers of the circuit design. One technique to improve the performance of the circuit design is through register retiming, which involves adjusting the placement of the registers back and forth across different groups of combinational logic to improve the maximum achievable clock signal frequency. Performing retiming on an initial circuit design may result in one or more revisions of the initial circuit design.
Certain computer-aided design (CAD) tools enable designers to choose various optimization options when generating revisions using retiming. For example, the optimization options may relate to synthesis, place-and-route, physical synthesis flow, and the like. Further, these computer-aided design tools enable designers to create multiple revisions with different settings and/or assignments. The sheer number of optimization options, settings, and/or assignments available may lead a designer to generate multiple revisions when searching for a satisfactory revision using the computer-aided design tool.
To aid in keeping track of the revisions, certain computer-aided design tools may provide reporting capabilities that compare the results of the revisions in a tabular format. However, the reporting capabilities do not provide insight on how certain optimization options, assignments, and/or settings influence the outcome (e.g., timing, power consumption, compilation) of the revisions as compared to each other. That is, current reporting capabilities are insufficient insofar as enabling determining which combination of optimization options, assignments, and/or settings is most desirable to meet the designer's circuit design criteria.